In a synchronous DRAM operating synchronously with a clock signal, the operation delay time from a change in column address signal to determination of read data can be defined as a CAS latency corresponding to a number of cycles of the clock signal. The operation delay time required for a data reading operation of the synchronous DRAM is determined by its circuit configuration uniquely. Therefore, the CAS latency is desired to be determined appropriately in accordance with the frequency of the clock signal to be used. In general, the higher the frequency of the clock signal being used, the larger will be the value of the CAS latency relatively speaking. A technique for controlling the output timing of an output buffer in accordance with a set value of the CAS latency is disclosed in Japanese Patent Laid-Open No. 215575/94 (U.S. Pat. No. 5,384,735), Japanese Patent Laid-Open No. 6-6846/99 and Japanese Patent Laid-open No. 302463/98 (U.S. Pat. No. 5,901,109), for example.
The present inventor has reviewed a clock synchronous memory having a much higher operation speed. That is, in response to a great enhancement of the data processing speed of a data processor, for example, a memory is provided for supporting a burst operation and pipeline burst access. However, this is not enough for increasing the operation speed. Thus, the present inventor has considered the possibility of changing the column address strobe signal once for every n cycles of the clock signal in order to divide information obtained through one column access operation for every clock signal cycle and output them to the outside. However, in that case, when the column address strobe signal is changed with a cycle shorter than n cycles of the clock signal, an error operation may occur in a regular memory operation. Especially, a rapidly operated memory control line is exposed to high frequency noise, for example. Therefore, the column address strobe signal can be influenced in actual practice. Thus, the inventor has found the effectiveness of providing a protective circuit within or in the vicinity of a semiconductor memory in order to satisfy a requirement that the column address strobe signal be changed once for every n cycles of the clock signal. Further, the inventor also clarified the fact that the protective circuit must be configured with respect to the CAS latency, when the CAS latency variable configuration is used.
It is an object of the present invention to provide a semiconductor integrated circuit, which can increase the speed of memory operations by means of an access specification for changing a column address strobe signal once per a predetermined plurality of cycles (n cycle hereinafter) of a clock signal.
It is another object of the present invention to provide a semiconductor integrated circuit which can prevent an erroneous operation from occurring when an external column address strobe signal does not satisfy the access specification for changing a column address strobe signal once for every n cycles of a clock signal.
These and other objects and novel features of the present invention will be apparent from the description herein and the accompanying drawings.
The present invention disclosed herein can be summarized as follows:
A semiconductor integrated circuit includes a memory block having a memory cell array, a row select circuit, a column select circuit, a serial/parallel converter circuit, a write amplifier, a main amplifier and a parallel/serial converter circuit. The memory cell array has a plurality of memory cells whose selector terminal is connected to a word line and whose data input/output terminal is connected to a bit line. The row select circuit selects a word line specified by a row address signal in response to a change in a row address strobe signal in synchronism with a clock signal. The column select circuit selects a plurality of bit lines in parallel, as specified by a column address signal in response to a change in a column address strobe signal, in synchronism with a clock signal. The serial/parallel converter circuit converts serial data from the outside to parallel data in synchronism with a clock signal. The write amplifier outputs, in parallel, an output from the serial/parallel converter circuit to the plurality of bit lines selected by the column select circuit. The main amplifier amplifies the parallel data output in parallel from the plurality of bit lines selected by the column select circuit. The parallel/serial converter circuit converts parallel data supplied from the main amplifier to serial data in synchronism with a clock signal. The column address strobe signal, which is changed in cycles as many as a plurality of times that of a clock signal cycle, is input to the memory block. A plurality of serial data, read out from the memory cell array and parallel/serial converted in synchronism with a clock signal cycle, are output for every cycle when the column address signal is changed. Parallel data, input to the memory block and serial/parallel converted in synchronous with the clock signal cycle, is written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows more rapid memory operation.
A serial data input path of the serial/parallel converter circuit and a serial data output path of the parallel/serial converter circuit may be provided independently. In a read operation, the parallel data is read out from the memory cell array in response to a change in the column address strobe signal, and then serial data is output from the memory block, where a time for parallel/serial conversion is necessary between the readout and the output. On the other hand, in a write operation, before parallel data is written into the memory cell array in response to the change in the column address strobe signal, serial data which has been input to the memory block in advance must be converted to parallel data completely in synchronism with input latch control signals. In this case, when a read operation is instructed subsequently to a write operation, an operation for inputting serial data for the write operation to the memory block sequentially in serial may need to be performed in parallel with an operation for outputting the serial data provided by the read operation from the memory block. That is, the timing for outputting serial data from the memory block and the timing for inputting serial data to the memory block may possibly overlap. As described above, providing the serial data input path and the serial data output path for the memory block independently allows avoidance of data collision in the case of overlapping of such processing. As a result, efficient processing can be achieved.
Further, a CAS input inhibiting circuit may be provided for inhibiting an input of a new change in the column address strobe signal in accordance with a CAS latency corresponding to the number of clock signal cycles during a period from one next to clock synchronous timing for the change in column address strobe signal to determination of a data input of the parallel/serial converter circuit. This CAS input inhibiting circuit, may be provided either external or internal of the memory block. Thus, when a column address strobe signal CAS from the outside does not satisfy the access specification that a column address strobe signal is changed once per n cycles of the clock signal, an error operation can be prevented.
A CAS latency control circuit may be adopted which can input a latency set signal so as to control the CAS latency in a variable manner. In this case, the CAS latency control circuit controls timing for latching parallel outputs from the main amplifier in the parallel/serial converter circuit.
When the CAS latency control circuit is adopted, the CAS input inhibiting circuit suppresses an input of a new change in the column address strobe signal until immediately before a lapse of a period corresponding to a CAS latency specified by the latency set signal. In that case, input inhibiting control on undesirable changes in CAS can be achieved even when the CAS latency is variable.